By NE NOW NEWS
Guwahati: International Business Machines Corporation (IBM) has unveiled a new semiconductor design that it says could pave the way for chips with up to 100 billion transistors packed onto a silicon die the size of a fingernail, marking what could become the world’s first chip technology below the one-nanometre threshold.
The company said its new NanoStack architecture is equivalent to a process node of around 0.7 nanometres (nm), significantly smaller than today’s industry-leading chips, which are based on roughly 2nm technology. However, IBM acknowledged that the technology remains in the research stage and is still several years away from commercial production.
According to IBM, laboratory tests showed the prototype delivering up to 50 per cent better performance than its own 2nm chip design while consuming 70 per cent less energy.
The announcement builds on IBM’s earlier 2nm breakthrough unveiled in 2021, when the company also reported substantial gains in computing performance and energy efficiency during testing.
Unlike conventional chip designs that primarily shrink transistors across a flat surface, IBM’s NanoStack architecture takes a different approach by stacking multiple layers of transistors vertically. The design aims to dramatically increase transistor density while improving computing power and reducing energy consumption.
“With our new NanoStack architecture, we’re not just making smaller transistors; we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow.
Transistors form the foundation of modern processors used in smartphones, laptops, gaming consoles, data centres and artificial intelligence systems. Increasing the number of transistors on a chip generally translates into greater computing capability.
For decades, semiconductor manufacturers have followed Moore’s Law—the observation that transistor density roughly doubles every two years. As chips have become increasingly compact, however, sustaining that pace has grown significantly more difficult, prompting companies to explore three-dimensional chip architectures instead of relying solely on shrinking transistor size.
Experts say IBM’s approach represents one of the industry’s most ambitious attempts to extend those limits.
Professor Alan Woodward, a computer scientist at the University of Surrey, likened IBM’s design to constructing a 100-storey skyscraper, while describing competing 3D chip technologies from companies such as Samsung and Intel as being closer to 30- to 50-storey buildings.
He noted that major engineering challenges remain, including heat management and preventing interference between densely stacked transistor layers, both of which are critical to ensuring reliable chip performance.
If successfully commercialised, the technology could enable faster and more energy-efficient processors for consumer electronics, cloud computing and next-generation artificial intelligence systems.